Encoding:

Format:

SHLLV[_S].PH 

SHLLV.PH   rd, rt, rs

SHLLV_S.PH rd, rt, rs

Purpose:

Shift Left Logical Variable Vector Pair Halfwords

Element-wise left shift of the two right-most independent halfwords in a vector data type by a variable number of bits, with optional saturation.

Description:

rd = sat16(rt31..16 << rs3..0) || sat16(rt15..0 << rs3..0)

The two halfword values in register rt are each independently shifted left by shift bits, inserting zeros into the leastsignificant bit positions emptied by the shift. In the saturating version of the instruction, if the shift results in an overflow the int ermediate result is satur ated to eit her the maximum positive or the minimum negative 16-bit value, depending on the sign of the original unshifted value. The two independent results are then written to the corresponding halfword elements of destination register rd.

The four least-significant bits of rs provide the shift value, interpreted as a four-bit unsigned integer; the remaining bits of rs are ignored.

This instruction writes a 1 to bit 22 in th e DSPControl register in the ouflag field if any of the left shift operations results in an overflow or saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

SHLLV.PH
   ValidateAccessToDSPResources()
   tempB15..0 = shift16Left( GPR[rt]31..16, GPR[rs]3..0 )
   tempA15..0 = shift16Left( GPR[rt]15..0, GPR[rs]3..0 )
   GPR[rd]31..0 = tempB15..0 || tempA15..0
SHLLV_S.PH
   ValidateAccessToDSPResources()
   tempB15..0 = sat16ShiftLeft( GPR[rt]31..16, GPR[rs]3..0 )
   tempA15..0 = sat16ShiftLeft( GPR[rt]15..0, GPR[rs]3..0 )
   GPR[rd]31..0 = tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled